1. Field of the Invention
This invention relates to a semiconductor memory device, and more particularly to an improved semiconductor memory device which ensures improvement in access time and power consumption.
2. Description of the Prior Art
FIG. 1 is a schematic block diagram showing a conventional semiconductor memory device. Interposed between each of pairs of bit lines 2a and 2b in complementary relationship are a plurality of memory cells 1 arranged in a matrix (rows by columns). The memory cells on the same row are connected to one and the same word line 3 which enables the same. Each of the word lines 3 is connected to a row decoder 4 which in turn is connected to a row address signal line 5 for decoding row address information. Respective ones of the bit lines 2a and 2b are connected to power supply terminals 7 by way of bit line loads 6a and 6b.
FIG. 2 is a circuit diagram detailing the memory cell 1 as shown in FIG. 1. One electrode of each of access transistors 10a and 10b is connected to the bit lines 2a or 2b, respectively, while its other electrode is connected to a store node 11a or 11b of the memory cell 1, respectively, the control electrode thereof being connected to a common word line 3. There are connected between the store nodes 11a and 11b inverter transistors 9a and 9b. Furthermore, the store nodes 11a and 11b are connected to the power supply terminals 7 through load elements 8a and 8b which typically comprise resistors.
The following will set forth operation of the semiconductor memory device described above when "high" level is written into the store node 11a and "low" level into the store node 11b, for example. If it is desired to read out the subject memory cell so written, then address information for that subject cell is fed to the address signal line 5 to activate the word line 3 on the row where there is disposed the subject cell. Upon activating the word line 3 the access transistors 10a and 10b become conductive. One of the inverter transistors 9b becomes conductive or ON because of the "high" level at the store node 11a, so that current flows through the bit line load 10b, the bit line 2b, the access transistor 10b and the inverter transistor 9b from the power supply terminal 7, thereby reading out the memory cell.
Since all of the memory cells on the same row are activated within the above arrangement of the semiconductor memory device, current (column current) flows from the power supply terminal to the memory cells via the bit lines over all of the columns, consumption current is remarkable especially in case of a static RAM of a large capacity with a good number of columns. A semiconductor memory device as illustrated in FIG. 3 has been suggested as one approach to minimize consumption current. In the semiconductor memory device illustrated therein, row decoders 4 are disposed at the center of the memory cell plane with each of word lines divided into a left-sided word line 3a and a right-sided word line 3b. AND gates 12a are for selection of the left-sided word lines 3a while another AND gates 12b are for selection of the right-sided word lines 3b. One input of each of the AND gates 12a and 12b is connected to the output of each of the row decoders 4 and the other input thereof is connected to a gate signal line 13a or 13b to which a gate enable signal is fed to open the associated gates.
By selectively applying the gate enable signal via the gate signal line 13a or 13b, only the word lines associated with a selected one of the left and right groups of the memory cells are activated. Accordingly, a path for column current is set up for only half of the columns of the matrix, whereby cutdown of power consumption is assured.
FIG. 4 shows a layout of another conventional semiconductor memory device designed based upon the concept as shown in FIG. 3. Generally, row decoders 4a and 4b are disposed for a plurality of columns and word lines 3a-3d are divided correspondingly, thereby reducing the number of DC current paths.
However, this conventional semiconductor memory device requires provision of a number of the row decoders, and hence, has the problem of increased chip area and deterioration of high speed performance and yield.